Professor Christos Dimitrakopoulos of our Chemical Engineering Department was a corresponding author of an article published online in the October 31 edition of Science, entitled “Layer-Resolved Graphene Transfer via Engineered Strain Layers.” The printed version will follow in the near future. The paper describes a groundbreaking method, in which high-quality, single crystalline graphene grown by subtractive epitaxy on a 4-inch diameter SiC wafer is exfoliated via the stress induced by a nickel film and subsequently transferred to a host substrate such as a standard silicon wafer.
This is very important, mainly for two reasons. First, it enables the fabrication of hybrid graphene/Si chips, while ensuring process compatibility with standard microelectronics fabrication facilities.
In such chips, standard silicon electronics functionality is embedded on the Si wafer, while ultrafast Radio Frequency (RF) transistors and circuits based on the transferred graphene provide ultrafast communication capabilities.
Second, it reduces the cost of large-area, single crystalline graphene by ca. 1000 times. The paper showed that the same SiC wafer can be used many times to grow and transfer graphene layers. It is estimated that the growth/transfer cycle can be repeated at least 1000 times, as less than 1 nm of SiC has to be consumed to make one graphene layer. Reusing multiple times an expensive SiC wafer (ca. $3000 ea.) dramatically reduces the cost of high quality single crystalline graphene. It should be noted that graphene grown on metal foils (e.g. Cu) is polycrystalline (comprises grain boundaries), and thus it is not a viable process for producing large-area single crystalline graphene. The same is true for graphene flakes exfoliated from graphite (their size is limited to a few microns).
As indicated in the Science article, graphene offers great potential for high-performance electrical and optical devices such as radio-frequency transistors, high-speed photodetectors, and optical modulators.
The most common approach used to build graphene devices is to grow polycrystalline graphene via chemical vapor deposition (CVD) on a thin metal foil, followed by dissolution (etching) of the foil and transfer of the graphene to the substrate of interest. This process can produce large areas of graphene with good thickness control. However, this graphene is often wrinkled because the metal foil substrate is rough and comprises cuts and tears and other defects due to the transfer process. Most importantly, the relative crystallographic orientation of the graphene domains is random because of the lack of registry with the substrate and the fact that the substrate itself is polycrystalline.
High-quality single crystalline graphene, on the other hand, can be grown epitaxially on the Si-face of SiC (0001) wafers. Because of the high cost of SiC wafers, and the need for integration of graphene devices with conventional Si integrated circuits (ICs), transfer of large area graphene from SiC surfaces to appropriate host substrates has been extremely desirable but had not been demonstrated until the publication of the subject paper.
To enable uniform and reproducible exfoliation and transfer of large area epitaxial graphene from a SiC surface onto another substrate, the authors developed and optimized a method for manipulating graphene layers with a single-atom-thickness precision based on the binding energy difference at specific interfaces. A 4-inch-diameter monolayer graphene sheet with a single crystalline orientation was grown on the Si-face of a SiC wafer. The graphene was completely exfoliated from the SiC wafer using an adhesive strained layer (nickel) with a predetermined internal stress, and a handling-layer (thermal release tape).
The graphene released from the SiC surface was then transferred onto a wafer, and then the thermal tape and Ni were removed. Electrical measurements on transistors and Hall bars proved that transferred graphene on SiO2/Si is as good as the pristine as-grown graphene on SiC. This technique enables the reuse of one SiC wafer for many growths/transfers, as demonstrated in detail in the supplementary part of the Science paper. (November 2013).